1 idt74fct823at/bt/ct/dt high-performance cmos bus interface register commercial temperature range september 1999 1999 integrated device technology, inc. dsc-5487/- c idt74fct823at/bt/ct/dt commercial temperature range high-performance cmos bus interface register description: the fct823t series is built using an advanced dual metal cmos technology. the fct823t series bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider address/data paths or buses carrying parity. the fct823t are 9-bit wide buffered registers with clock enable ( en ) and clear ( clr ) C ideal for parity bus interfacing in high-performance microprogrammed systems. the fct823t high-performance interface family can drive large capaci- tive loads, while providing low-capacitance bus loading at both inputs and outputs. all inputs have clamp diodes and all outputs are designed for low- capacitance bus loading in high-impedance state. functional block diagram d cp q q cl d cp q q cl d 0 d n y 0 y n en clr cp oe features: - low input and output leakage 1 a (max.) - extended commercial range of C40c to +85c - cmos power levels - true ttl input and output compatibility v oh = 3.3v (typ.) v ol = 0.3v (typ.) - meets or exceeds jedec standard 18 specifications - product available in radiation tolerant and radiation enhanced versions - available in pdip, soic, ssop, and qsop packages - a, b, c and d speed grades - high drive outputs (-15ma i oh , 48ma i ol ) - power off disable outputs permit live insertion
2 commercial temperature range idt74fct823at/bt/ct/dt high-performance cmos bus interface register pin configuration note: 1. h = high l = low x = dont care nc = no change - = low-to-high transition z = high-impedance 2 3 1 20 19 18 15 16 9 10 d 6 d 7 d 2 d 5 d 3 d 4 d 8 23 22 24 21 17 5 6 7 4 p24-1 d24-1 so24-2 so24-7 so24-8 8 d 0 v cc cp oe 13 14 11 12 d 1 gnd clr y 6 y 7 y 2 y 5 y 3 y 4 y 8 y 0 y 1 en pdip/ soic/ ssop/ qsop top view pin description names i/o description d i i the d flip-flop data inputs. clr i when the clear input is low and oe is low, the q i outputs are low. when the clear input is high, data can be entered into the register. cp i clock pulse for the register; enters data into the register on the low-to-high transition. y i o the register 3-state outputs. en i clock enable. when the clock enable is low, data on the d i input is transferred to the q i output on the low-to-high clock transition. when the clock enable is high, the q i outputs do not change state, regardless of the data or clock input transitions. oe i output control. when the oe input is high, the y i outputs are in the high-impedance state. when the oe input is low, the true register data is present at the y i outputs. function table (1) inputs internal/ outputs oe clr en d i cp q i y i function h h h h l l l h - - l h z z high z h l l l x x x x x x l l z l clear h l h h h h x x x x nc nc z nc hold h h l l h h h h l l l l l h l h - - - - l h l h z z l h load absolute maximum ratings (1) symbol rating max. unit v term (2) terminal voltage with respect to gnd C0.5 to +7 v v term (3) terminal voltage with respect to gnd C0.5 to v cc +0.5 v t stg storage temperature C65 to +150 c i out dc output current C65 to +120 ma 8t-link notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. no terminal voltage may exceed vcc by +0.5v unless otherwise noted. 2. inputs and vcc terminals only. 3. outputs and i/o terminals only. capacitance (t a = +25 o c, f = 1.0mhz) symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 6 10 pf c out output capacitance v out = 0v 8 12 pf 8t-link note: 1. this parameter is measured at characterization but not tested.
3 idt74fct823at/bt/ct/dt high-performance cmos bus interface register commercial temperature range notes: 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at vcc = 5.0v, +25c ambient. 3. not more than one output should be shorted at one time. duration of the short circuit test should not exceed one second. 4. the test limit for this parameter is 5a at t a = C55c. 5. this parameter is guaranteed but not tested. dc electrical characteristics over operating range following conditions apply unless otherwise specified: commercial: t a = C40c to +85c, v cc = 5.0v 5% symbol parameter test conditions (1) min. typ. (2) max. unit v ih input high level guaranteed logic high level 2 v v il input low level guaranteed logic low level 0.8 v i i h input high current (4) v cc = max. v i = 2.7v 1 a i i l input low current (4) v i = 0.5v 1 i ozh high impedance output current v cc = max. v o = 2.7v 1 a i ozl (3-state output pins) (4) v o = 0.5v 1 i i input high current (4) v cc = max., v i = v cc (max.) 1 a v ik clamp diode voltage v cc = min., i in = C18ma C0.7 C1.2 v v h input hysteresis 200 mv i cc quiescent power supply current v cc = max., v in = gnd or v cc 0.01 1 ma output drive characteristics symbol parameter test conditions (1) min. typ. (2) max. unit v oh output high voltage v cc = min. i oh = C8ma 2.4 3.3 v v in = v ih or v il i oh = C15ma 2 3 v ol output low voltage v cc = min. i ol = 48ma 0.3 0.5 v v in = v ih or v il i os short circuit current v cc = max., v o = gnd (3) C60 C120 C225 ma i off input/output power off leakage (5) v cc = 0v, v in or v o 4.5v 1a
4 commercial temperature range idt74fct823at/bt/ct/dt high-performance cmos bus interface register power supply characteristics symbol parameter test conditions (1) min. typ. (2) max. unit d i cc quiescent power supply current ttl inputs high v cc = max. v in = 3.4v (3) 0.5 2 ma i ccd dynamic power supply current (4) v cc = max. outputs open oe = en = gnd one input toggling 50% duty cycle v in = v cc v in = gnd 0.15 0.25 ma/ mhz i c total power supply current (6) v cc = max. outputs open f cp = 10mhz 50% duty cycle v in = v cc v in = gnd 1.53.5ma oe = en = gnd one bit toggling at fi = 5mhz 50% duty cycle v in = 3.4v v in = gnd 25.5 v cc = max. outputs open f cp = 10mhz 50% duty cycle v in = v cc v in = gnd 3.87.3 (5) oe = en = gnd eight bits toggling at fi = 2.5mhz 50% duty cycle v in = 3.4v v in = gnd 6 16.3 (5) notes: 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at v cc = 5.0v, +25c ambient. 3. per ttl driven input (v in = 3.4v). all other inputs at v cc or gnd. 4. this parameter is not directly testable, but is derived for use in total power supply calculations. 5. values for these conditions are examples of the i cc formula. these limits are guaranteed but not tested. 6. i c = i quiescent + i inputs + i dynamic i c = i cc + d i cc d h n t + i ccd (f cp/ 2 + f i n i ) i cc = quiescent current d i cc = power supply current for a ttl high input (v in = 3.4v) d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an input transition pair (hlh or lhl) f cp = clock frequency for register devices (zero for non-register devices) f i = input frequency n i = number of inputs at f i all currents are in milliamps and all frequencies are in megahertz.
5 idt74fct823at/bt/ct/dt high-performance cmos bus interface register commercial temperature range notes: 1. see test circuit and waveforms. 2. minimum limits are guaranteed but not tested on propagation delays. 3. this parameter is guaranteed but not tested. 4. this condition is guaranteed but not tested. switching characteristics over operating range fct823at fct823bt fct823ct fct823dt symbol parameter condition (1) min . (2) max. min . (2) max. min . (2) max. min . (2) max. unit t plh t phl propagation delay cp to y i ( oe = low) c l = 50pf r l = 500 w 1.5 10 1.5 7.5 1.5 6 1.5 5 ns c l = 300pf (4) r l = 500 w 1.5 20 1.5 15 1.5 12.5 1.5 8.5 t su set-up time high or low d i to cp c l = 50pf r l = 500 w 4332 ns t h hold time high or low d i to cp 2 1.5 1.5 1 ns t su set-up time high or low en to cp 4333 ns t h hold time high or low en to cp 2000ns t phl propagation delay, clr to y i 1.5 14 1.5 9 1.5 8 1.5 5 ns t rem recovery time clr to cp 6663ns t w clock pulse width high or low 7663 ns t w clr pulse width low 6663ns t pzh t pzl output enable time oe to y i c l = 50pf r l = 500 w 1.5 12 1.5 8 1.5 7 1.5 4.8 ns c l = 300pf (4) r l = 500 w 1.5 23 1.5 15 1.5 12.5 1.5 9 t phz t plz output disable time oe to y i c l = 5pf (4) r l = 500 w 1.5 7 1.5 6.5 1.5 6 1.5 4 ns c l = 50pf r l = 500 w 1.5 8 1.5 7.5 1.5 6.5 1.5 4
6 commercial temperature range idt74fct823at/bt/ct/dt high-performance cmos bus interface register pulse generator r t d.u.t. v cc v in c l v out 50pf 500 w 500 w 7.0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v data input timing input asynchronous control preset clear etc. synchronous control t su t h t rem t su t h high-low-high pulse low-high-low pulse t w 1.5v 1.5v same phase input transition 3v 1.5v 0v 1.5v v oh t plh output opposite phase input transition 3v 1.5v 0v t plh t phl t phl v ol control input 3v 1.5v 0v 3.5v 0v output normally low output normally high switch closed switch open v ol 0.3v 0.3v t plz t pzl t pzh t phz 3.5v 0v 1.5v 1.5v enable disable v oh preset clear clock enable etc. octal link octal link octal link octal link octal link test cir cuits and w a veforms propagation delay test circuits for all outputs enable and disable times set-up, hold, and release times pulse width switch position test switch open drain disable low closed enable low all other tests open 8-link definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator. notes: 1. diagram shown for input control enable-low and input control disable- high 2. pulse generator for all pulses: rate 1.0mhz; t f 2.5ns; t r 2.5ns
7 idt74fct823at/bt/ct/dt high-performance cmos bus interface register commercial temperature range corporate headquarters for sales: 2975 stender way 800-345-7015 or 408-727-6116 santa clara, ca 95054 fax: 408-492-8674 www.idt.com* *to search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. the idt logo is a registered trademark of integrated device technology, inc. ordering information xx temp. range xxxx device type x package x process blank p d so py q 823at 823bt 823ct 823dt commercial plastic dip (p24-1) cerdip (d24-1) small outline ic (so24-2) shrink small outline package (so24-7) quarter-size small outline package (so24-8) bus interface register 74 - 40c to +8 5c idt fct
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